EETimes - New FPGA-based USB 3.0 SuperSpeed Device Controller From SLS
CP220x Ethernet Controllers - Silicon Labs
Archimago's Musings: MEASUREMENTS: Computer USB port noise, USB hubs and the 8kHz PHY Microframe Packet Noise
HSIC USB 2.0 PHY IP
Figure 2 from Verilog synthesis of USB 2.0 full-speed device PHY IP | Semantic Scholar
USB 3.0/2.0 Combo PHY IP for SoC Designs | Cadence IP
USB-IF certified solutions for USB type-C and Power Delivery - STMicroelectronics
usb3300-ezk hi speed usb host or device phy with ulpi low pin interface
MB86C311A TQFP-64 chip with hardware AES USB 3.0 PHY (Device) USB 3.0 IC | eBay
USB 3.0 PHY for SoC Designs | Cadence IP
Standalone USB Transceiver Chip - EEWeb
ULPI - Kcchao
TUSB1210 data sheet, product information and support | TI.com
USB 2.0 PHY for SoC Designs | Cadence IP
USB 2.0 PHY IP Core Device Host OTG Hub in TSMC, 28HPC, 40LP /LL, UMC, 40LP, 28HPC, SMIC 14SF, SF, 55LL, 40LL - T2M-IP
USB 2.0/HSIC PHY (Host/Device/OTG/Hub) - IP Solution - INNOSILICON
USB 2.0 Full High Speed Solution | NXP Semiconductors
USB Communicator
Usb3300 High Speed Usb Host Device Or Otg Phy 2.0 3.3v T/r 32-pin Qfn Ep Ic Chip Usb3300-ezk-tr - Buy Usb3300-ezk-tr,Usb3300,Usb3300 High Speed Usb Host Device Or Otg Phy 2.0 3.3v T/r
USB 2.0 PHY IP core | Arasan Chip Systems
Mixed-Signal Verification for USB 2.0 Physical Layer IP
DWTB: USB High Speed Inter-Chip (HSIC) IP: What is it? And why should I use it?
XR2280x Hi-Speed USB to 10/100 Ethernet Bridge ICs - MaxLinear | Mouser